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72 Mb (2M x 36 & 4M x 18) 7 QUADP (Burst of 4) Synchronous SRAMs Q
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I
May 2009
Features
* 2M x 36 or 4M x 18. * On-chip delay-locked loop (DLL) for wide data valid window. * Separate read and write ports with concurrent read and write operations. * Synchronous pipeline read with late write operation. * Double data rate (DDR) interface for read and write input ports. * Fixed 4-bit burst for read and write operations. * Clock stop support. * Two input clocks (K and K) for address and control registering at rising edges only. * Two echo clocks (CQ and CQ) that are delivered simultaneously with data. * +1.8V core power supply and 1.5, 1.8V VDDQ, used with 0.75, 0.9V VREF. * HSTL input and output levels. * Registered addresses, write and read controls, byte writes, data in, and data outputs. * Full data coherency. * Boundary scan using limited set of JTAG 1149.1 functions. * Byte write capability. * Fine ball grid array (FBGA) package - 15mm x 17mm body size - 1mm pitch - 165-ball (11 x 15) array * Programmable impedance output drivers via 5x user-supplied precision resistor.
Description
The 72Mb IS61QDPB42M36 and IS61QDPB44M18 are synchronous, high-performance CMOS static random access memory (SRAM) devices. These SRAMs have separate I/Os, eliminating the need for high-speed bus turnaround. The rising edge of K clock initiates the read/write operation, and all internal operations are self-timed. Refer to the Timing Reference Diagram for Truth Table on page 8 for a description of the basic operations of these QUADP (Burst of 4) SRAMs. Read and write addresses are registered on alternating rising edges of the K clock. Reads and writes are performed in double data rate. The following are registered internally on the rising edge of the K clock: * * * * * Read/write address Read enable Write enable Byte writes for burst addresses 1 and 3 Data-in for burst addresses 1 and 3 * Byte writes for burst addresses 2 and 4 * Data-in for burst addresses 2 and 4 Byte writes can change with the corresponding datain to enable or disable writes on a per-byte basis. An internal write buffer enables the data-ins to be registered one cycle after the write address. The first data-in burst is clocked one cycle later than the write command signal, and the second burst is timed to the following rising edge of the K clock. Two full clock cycles are required to complete a write operation. The device is operated with a single +1.8V power supply and is compatible with HSTL I/O interfaces.
The following are registered on the rising edge of the K clock:
Integrated Silicon Solution, Inc.
Rev. A 05/14/09
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72 Mb (2M x 36 & 4M x 18) QUADP (Burst of 4) Synchronous SRAMs
x36 FBGA Pinout (Top View)
1 A B C D E F G H J K L M N P R CQ Q27 D27 D28 Q29 Q30 D30 Doff D31 Q32 Q33 D33 D34 Q35 TDO 2 NC/SA* Q18 Q28 D20 D29 Q21 D22 VREF Q31 D32 Q24 Q34 D26 D35 TCK 3 SA D18 D19 Q19 Q20 D21 Q22 VDDQ D23 Q23 D24 D25 Q25 Q26 SA 4 W SA VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS SA SA 5 BW2 BW3 SA VSS VSS VDD VDD VDD VDD VDD VSS VSS SA SA SA 6 K K NC VSS VSS VSS VSS VSS VSS VSS VSS VSS SA NC NC 7 BW1 BW0 SA VSS VSS VDD VDD VDD VDD VDD VSS VSS SA SA SA 8 R SA VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS SA SA 9 SA D17 D16 Q16 Q15 D14 Q13 VDDQ D12 Q12 D11 D10 Q10 Q9 SA 10 NC/SA* Q17 Q7 D15 D6 Q14 D13 VREF Q4 D3 Q11 Q1 D9 D0 TMS 11 CQ Q8 D8 D7 Q6 Q5 D5 ZQ D4 Q3 Q2 D2 D1 Q0 TDI
Note: *The following pins are reserved for higher densities: 10A for 144Mb, and 2A for 288Mb. QVLD pin (6P) is not supported.
x18 FBGA Pinout (Top View)
1 A B C D E F G H J K L M N P R CQ NC NC NC NC NC NC Doff NC NC NC NC NC NC TDO 2 NC/SA* Q9 NC D11 NC Q12 D13 VREF NC NC Q15 NC D17 NC TCK 3 SA D9 D10 Q10 Q11 D12 Q13 VDDQ D14 Q14 D15 D16 Q16 Q17 SA 4 W SA VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS SA SA 5 BW1 NC SA VSS VSS VDD VDD VDD VDD VDD VSS VSS SA SA SA 6 K K NC VSS VSS VSS VSS VSS VSS VSS VSS VSS SA NC NC 7 NC BW0 SA VSS VSS VDD VDD VDD VDD VDD VSS VSS SA SA SA 8 R SA VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS SA SA 9 SA NC NC NC NC NC NC VDDQ NC NC NC NC NC NC SA 10 SA NC Q7 NC D6 NC NC VREF Q4 D3 NC Q1 NC D0 TMS 11 CQ Q8 D8 D7 Q6 Q5 D5 ZQ D4 Q3 Q2 D2 D1 Q0 TDI
Note: *The following pins are reserved for higher densities: 2A for 144Mb. QVLD pin (6P) is not supported.
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Integrated Silicon Solution, Inc.
Rev. A 05/14/09
72 Mb (2M x 36 & 4M x 18) QUADP (Burst of 4) Synchronous SRAMs
Pin Description
Symbol K, K . CQ, CQ Doff SA SA D0-D8 D9-D17 D18-D26 D27-D35 Q0-Q8 Q9-Q17 Q18-Q26 Q27-Q35 D0-D8 D9-D17 Q0-Q8 Q9-Q17 W R 11A, 1A 1H 3A, 9A, 4B, 8B, 5C, 7C, 5N, 6N, 7N, 4P, 5P, 7P, 8P, 3R, 4R, 5R, 7R, 8R, 9R Output echo clock. DLL disable when low. 2M x 36 address inputs. 6B, 6A Pin Number Input clock. Description
3A, 9A, 10A, 4B, 8B, 5C, 7C, 5N, 6N, 7N, 4P, 5P, 7P, 8P, 3R, 4R, 4M x 18 address inputs. 5R, 7R, 8R, 9R 10P, 11N, 11M, 10K, 11J, 11G, 10E, 11D, 11C 10N, 9M, 9L, 9J, 10G, 9F, 10D, 9C, 9B 3B, 3C, 2D, 3F, 2G, 3J, 3L, 3M, 2N 1C, 1D, 2E, 1G, 1J, 2K, 1M, 1N, 2P 11P, 10M, 11L, 11K, 10J, 11F, 11E, 10C, 11B 9P, 9N, 10L, 9K, 9G, 10F, 9E, 9D, 10B 2B, 3D, 3E, 2F, 3G, 3K, 2L, 3N, 3P 1B, 2C, 1E, 1F, 2J, 1K, 1L, 2M, 1P 10P, 11N, 11M, 10K, 11J, 11G, 10E, 11D, 11C 3B, 3C, 2D, 3F, 2G, 3J, 3L, 3M, 2N 11P, 10M, 11L, 11K, 10J, 11F, 11E, 10C, 11B 2B, 3D, 3E, 2F, 3G, 3K, 2L, 3N, 3P 4A 8A
2M x 36 data inputs.
2M x 36 data outputs.
4M x 18 data inputs. 4M x 18 data outputs. Write control, active low. Read control, active low. 2M x 36 byte write control, active low. 4M x 18 byte write control, active low. Input reference level. Power supply. Output power supply. Ground. Output driver impedance control. IEEE 1149.1 test inputs (1.8V LVTTL levels). IEEE 1149.1 test output (1.8V LVTTL level).
BW0, BW1, BW2, BW3 7B, 7A, 5A,5B BW0, BW1 VREF VDD VDDQ VSS ZQ TMS, TDI, TCK TDO NC for x36 NC for x18 7B, 5A 2H, 10H 5F, 7F, 5G, 7G, 5H, 7H, 5J, 7J, 5K, 7K 4E,8E,4F,8F,4G,8G,3H,4H,8H,9H,4J,8J,4K,8K,4L,8L 4C, 8C, 4D, 5D, 6D, 7D, 8D, 5E, 6E, 7E, 6F, 6G, 6H, 6J, 6K, 5L, 6L, 7L, 4M, 5M, 6M, 7M, 8M, 4N, 8N 11H 10R, 11R, 2R 1R 2A, 10A, 6C, 6P, 6R 2A, 7A, 1B, 5B, 9B, 10B, 1C, 2C, 6C, 9C, 1D, 9D, 10D, 1E, 2E, 9E, 1F, 9F, 10F, 1G, 9G, 10G, 1J, 2J, 9J, 1K, 2K, 9K, 1L, 9L, 10L, 1M, 2M, 9M, 1N, 9N, 10N, 1P, 2P, 6P, 9P, 6R
Integrated Silicon Solution, Inc.
Rev. A 05/14/09
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72 Mb (2M x 36 & 4M x 18) Q QUADP (Burst of 4) Synchronous SRAMs
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Block Diagram
D (Data-In)
36 (o r 18)
Data Reg
72 (or 36 )
72 (or 36)
Wr ite Driver Output Reg
72 (or 36) 144 (or 72)
Wr ite/Read Decode
Output Select
Address
Output Driver
19 (o r 20)
Add Reg
19 (or 20 )
36 ( or 18) Q (D ata- Out) CQ, CQ (Ech o Cloc k Out)
R W BW x K K C
Doff 4 (or 2)
Control Logic
2M x 36 (4M x 18) Memory Array
S ense Am ps
72 (or 36)
Cloc k Gen
Select Output Control
SRAM Features
Read Operations The SRAM operates continuously in a burst-of-four mode. Read cycles are started by registering R in active low state at the rising edge of the K clock. R can be activated every other cycle because two full cycles are required to complete the burst of four in DDR mode. A set of free-running echo clocks, CQ and CQ, are produced internally with timings identical to the data-outs. The echo clocks can be used as data capture clocks by the receiver device. The data corresponding to the first address is clocked 2.5 cycles later by the rising edge of the K clock. The data corresponding to the second burst is clocked 3 cycles later by the following rising edge of the K clock. The third data-out is clocked by the subsequent rising edge of the K clock, and the fourth data-out is clocked by the subsequent rising edge of the K clock. A NOP operation (R is high) does not terminate the previous read. Write Operations Write operations can also be initiated at every other rising edge of the K clock whenever W is low. The write address is provided simultaneously. Again, the write always occurs in bursts of four. The write data is provided in a `late write' mode; that is, the data-in corresponding to the first address of the burst, is presented 1 cycle later or at the rising edge of the following K clock. The data-in corresponding to the second write burst address follows next, registered by the rising edge of K. The third data-in is clocked by the subsequent rising edge of the K clock, and the fourth data-in is clocked by the subsequent rising edge of the K clock.
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Integrated Silicon Solution, Inc.
Rev. A 05/14/09
72 Mb (2M x 36 & 4M x 18) Q QUADP (Burst of 4) Synchronous SRAMs
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The data-in provided for writing is initially kept in write buffers. The information in these buffers is written into the array on the third write cycle. A read cycle to the last two write addresses produces data from the write buffers. The SRAM maintains data coherency. During a write, the byte writes independently control which byte of any of the four burst addresses is written (see X18/X36 Write Truth Tables on pages 10 - 11 and Timing Reference Diagram for Truth Table on page 8). Whenever a write is disabled (W is high at the rising edge of K), data is not written into the memory. RQ Programmable Impedance An external resistor, RQ, must be connected between the ZQ pin on the SRAM and VSS to enable the SRAM to adjust its output driver impedance. The value of RQ must be 5x the value of the intended line impedance driven by the SRAM. For example, an RQ of 250 results in a driver impedance of 50. The allowable range of RQ to guarantee impedance matching is between 175 and 350, with the tolerance described in Programmable Impedance Output Driver DC Electrical Characteristics on page 16. The RQ resistor should be placed less than two inches away from the ZQ ball on the SRAM module. The capacitance of the loaded ZQ trace must be less than 3 pF. The ZQ pin can also be directly connected to VDDQ to obtain a minimum impedance setting. ZQ must never be connected to VSS. Programmable Impedance and Power-Up Requirements Periodic readjustment of the output driver impedance is necessary as the impedance is greatly affected by drifts in supply voltage and temperature. At power-up, the driver impedance is in the middle of allowable impedances values. The final impedance value is achieved within 2048 clock cycles. Depth Expansion Separate input and output ports enable easy depth expansion, as each port can be selected and deselected independently. Read and write operations can occur simultaneously without affecting each other. Also, all pending read and write transactions are always completed prior to deselecting the corresponding port.
Integrated Silicon Solution, Inc.
Rev. A 05/14/09
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72 Mb (2M x 36 & 4M x 18) QUADP (Burst of 4) Synchronous SRAMs
Application Example
R=250
SRAM #1 D
R
ZQ R=250 CQ CQ
SRAM #4 D SA R W BW0 BW1
ZQ
CQ CQ
Vt
Q
Q KK
SA
R W BW0 BW1
KK
Data In Data Out Address R W BW Memory Controller Source CLK Source CLK
Vt R Vt
R=50 Vt=VREF
SRAM1 Input CQ SRAM1 Input CQ SRAM4 Input CQ SRAM4 Input CQ
Power-Up and Power-Down Sequences
The following sequence is used for power-up: 1. The power supply inputs must be applied in the following order while keeping Doff in LOW logic state: 1) VDD 2) VDDQ 3) VREF 2. Start applying stable clock inputs (K, K, C, and C). 3. After clock signals have stabilized, change Doff to HIGH logic state. 4. Once the Doff is switched to HIGH logic state, wait an additional 1024 clock cycles to lock the DLL.
NOTES: 1. The power-down sequence must be done in reverse of the power-up sequence. 2. VDDQ can be allowed to exceed VDD by no more than 0.6V. 3. VREF can be applied concurrently with VDDQ.
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Integrated Silicon Solution, Inc.
Rev. A 05/14/09
72 Mb (2M x 36 & 4M x 18) QUADP (Burst of 4) Synchronous SRAMs Q
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State Diagram
Power-Up
Read NOP Read Load New Read Address D count = 0 Always
Read
Write
Write NOP Write Load New Write Address D count = 0 Always Write D count = 2
Read D count = 2
Write D count = 2
Read D count = 2
DDR-II Read D count = D count + 1 Read D count = 1 Always
DDR-II Write D count = D count + 1 Write D count = 1 Always
Increment Read Address
Increment Write Address
Notes: 1. Internal burst counter is fixed as four-bit linear; that is, when first address is A0+0, next internal burst addresses are A0+1, A0+2, and A0+3 . 2. Read refers to read active status with R = low. Read refers to read inactive status with R = high. 3. Write refers to write active status with W = low. Write refers to write inactive status with W = high. 4. The read and write state machines can be active simultaneously. 5. State machine control timing sequence is controlled by K.
The Timing Reference Diagram for Truth Table on page 8 is helpful in understanding the clock and write truth tables, as it shows the cycle relationship between clocks, address, data in, data out, and controls. All read and write commands are issued at the beginning of cycle "t".
Integrated Silicon Solution, Inc.
Rev. A 05/14/09
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72 Mb (2M x 36 & 4M x 18) QUAD (Burst of 4) Synchronous SRAMs
Timing Reference Diagram for Truth Table
Cycle
t Read A
t+1 Write B
t+2
t+3
t+4
K Clock K Clock R W BWX Address Data-In Data-Out A B DB DB+1 DB+2 QA DB+3 QA+1 QA+2 QA+3
CQ Clock CQ Clock
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Integrated Silicon Solution, Inc.
Rev. A 05/14/09
72 Mb (2M x 36 & 4M x 18) QUADP (Burst of 4) Synchronous SRAMs Q
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Data Out DB+3 QA Previous State High-Z Dout at K (t + 2.5) X QA+1 Previous State High-Z QA+2 Previous State High-Z QA+3 Previous State High-Z Dout at K (t + 4.0) X
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Clock Truth Table (Use the following table with the Timing Reference Diagram for Truth Table.)
Clock Mode K Stop Clock No Operation (NOP) Read B Stop LH L H L H R X H L W X H X DB DB+1 DB+2 Previous Previous Previous Previous State State State State X X Din at K (t + 1) X X Din at K (t + 1.5) X X Din at K (t + 2) X X Din at K (t + 2.5) Controls Data In
Dout at K Dout at K (t + 3.0) (t + 3.5) X X
Write A
X
L
Notes: 1. Internal burst counter is always fixed as four-bit. 2. X = "don't care"; H = logic "1"; L = logic "0". 3. A read operation is started when control signal R is active low 4. A write operation is started when control signal W is active low. Before entering into stop clock, all pending read and write commands must be completed. 5. Consecutive read or write operations can be started only at every other K clock rising edge. If two read or write operations are issued in consecutive K clock rising edges, the second one will be ignored. 6. If both R and W are active low after a NOP operation, the write operation will be ignored. 7. For timing definitions, refer to the AC Characteristics on page 17. Signals must have AC specifications at timings indicated in parenthesis with respect to switching clocks K and K.
Integrated Silicon Solution, Inc.
Rev. A 05/14/09
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72 Mb (2M x 36 & 4M x 18) Q QUADP (Burst of 4) Synchronous SRAMs
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BW2 BW3 H H L H L H H H L H L H H H L H L H H H L H L H H H H L L H H H H L L H H H H L L H H H H L L H DB D0-8 (t+1) D9-17 (t+1) D18-26 (t+1) D27-35 (t+1) D0-35 (t+1) Don't care D0-8 (t+1.5) D9-17 (t+1.5) D18-26
(t+1.5)
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X36 Write Truth Table Use the following table with the Timing Reference Diagram for Truth Table on
page 8.
Operation Write Byte 0 Write Byte 1 Write Byte 2 Write Byte 3 Write All Bytes Abort Write Write Byte 0 Write Byte 1 Write Byte 2 Write Byte 3 Write All Bytes Abort Write Write Byte 0 Write Byte 1 Write Byte 2 Write Byte 3 Write All Bytes Abort Write Write Byte 0 Write Byte 1 Write Byte 2 Write Byte 3 Write All Bytes Abort Write K(t+1) K(t+1.5) K(t+2) K(t+2.5) BW0 LH LH LH LH LH LH LH LH LH LH LH LH LH LH LH LH LH LH LH LH LH LH LH LH L H H H L H L H H H L H L H H H L H L H H H L H BW1 H L H H L H H L H H L H H L H H L H H L H H L H DB+1 DB+2 DB+3
D27-35
(t+1.5)
D0-35 (t+1.5) Don't care D0-8 (t+2) D9-17 (t+2) D18-26
(t+2)
D27-35
(t+2)
D0-35 (t+2) Don't care D0-8 (t+2.5) D9-17 (t+2.5) D18-26 (t+2.5) D27-35 (t+2.5) D0-35 (t+2.5) Don't care
Notes; 1. For all cases, W needs to be active low during the rising edge of K occurring at time t. 2. For timing definitions refer to the AC Characteristics on page 17. Signals must have AC specifications with respect to switching clocks K and K.
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Integrated Silicon Solution, Inc.
Rev. A 05/14/09
3 72 Mb (2M x 36 & 4M x 18) QQUADP (Burst of 4) Synchronous SRAMs
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DB+1 DB+2 DB+3
(R)
X18 Write Truth Table Use the following table with the Timing Reference Diagram for Truth Table on
page 8.
Operation Write Byte 0 Write Byte 1 Write All Bytes Abort Write Write Byte 0 Write Byte 1 Write All Bytes Abort Write Write Byte 0 Write Byte 1 Write All Bytes Abort Write Write Byte 0 Write Byte 1 Write All Bytes Abort Write K(t+1) K(t+1.5) K(t+2) K(t+2.5) BW0 LH LH LH LH LH LH LH LH LH LH LH LH LH LH LH LH L H L H L H L H L H L H L H L H BW1 H L L H H L L H H L L H H L L H DB D0-8 (t+1) D9-17 (t+1) D0-17 (t+1) Don't care D0-8 (t+1.5) D9-17 (t+1.5) D0-17 (t+1.5) Don't care D0-8 (t+2) D9-17 (t+2) D0-17 (t+2) Don't care D0-8 (t+2.5) D9-17 (t+2.5) D0-17 (t+2.5) Don't care
Notes; 1. For all cases. W needs to be active low during the rising edge of K occurring at time t. 2. For timing definitions refer to the AC Characteristics on page 17. Signals must have AC specifications with respect to switching clocks K and K.
Integrated Silicon Solution, Inc.
Rev. A 05/14/09
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72 Mb (2M x 36 & 4M x 18) QUADP (Burst of 4) Synchronous SRAMs Q
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Symbol VDD VDDQ VIN VDOUT TA TJ TSTG Rating -0.5 to 2.9V -0.5 to 2.9V -0.5 to VDD+0.3V -0.5 to 2.6 0 to 70 110 -55 to +125 Units V V V V C C C
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Absolute Maximum Ratings
Item Power supply voltage Output power supply voltage Input voltage Data out voltage Operating temperature Junction temperature Storage temperature
Note: Stresses greater than those listed in this table can cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this datasheet is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
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Integrated Silicon Solution, Inc.
Rev. A 05/14/09
72 Mb (2M x 36 & 4M x 18) QUADP (Burst of 4) Synchronous SRAMs
Recommended DC Operating Conditions (TA = 0 to +70 C)
Parameter Supply voltage Output driver supply voltage Input high voltage Input low voltage Input reference voltage Clocks signal voltage 1. 2. 3. 4. 5. Symbol VDD VDDQ VIH VIL VREF VIN - CLK Minimum 1.8 - 5% 1.4 VREF +0.1 -0.2 0.68 -0.2 Typical Maximum 1.8 + 5% 1.9 VDDQ + 0.2 VREF - 0.1 0.95 VDDQ + 0.2 Units V V V V V V Notes 1 1 1, 2 1, 3 1, 5 1, 4
All voltages are referenced to VSS. All VDD, VDDQ, and VSS pins must be connected. VIH(Max) AC = See 0vershoot and Undershoot Timings. VIL(Min) AC = See 0vershoot and Undershoot Timings. VIN-CLK specifies the maximum allowable DC excursions of each clock (K and K). Peak-to-peak AC component superimposed on VREF may not exceed 5% of VREF.
0vershoot and Undershoot Timings
20% Min Cycle Time
VDDQ+0.6V
VIL(Min) AC Undershoot Timing
VDDQ
GND
VIH(Max) AC
Overshoot Timing
GND-0.6V 20% Min Cycle Time
PBGA Thermal Characteristics
Item Thermal resistance junction to ambient (airflow = 1m/s) Thermal resistance junction to case Thermal resistance junction to pins Symbol RJA RJC RJB Rating 18.6 4.3 1.77 Units C/W C/W C/W
Integrated Silicon Solution, Inc.
Rev. A 05/14/09
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72 Mb (2M x 36 & 4M x 18) QUADP (Burst of 4) Synchronous SRAMs
Capacitance (TA = 0 to + 70 C, VDD = 1.8V -5%, +5%, f = 1MHz)
Parameter Input capacitance Data-in capacitance (D0-D35) Data-out capacitance (Q0-Q35) Clocks Capacitance (K, K) Symbol CIN CDIN COUT Test Condition VIN = 0V VDIN = 0V VOUT = 0V VCLK = 0V Maximum 4 4 4 4 Units pF pF pF pF
C CLK
DC Electrical Characteristics (TA = 0 to + 70 C, VDD = 1.8V -5%, +5%)
Parameter Symbol Minimum Maximum 1050 950 -- 850 750 1000 -- 900 800 700 -- -2 -2 VDDQ -.4 VSS -100 400 +2 +2 VDDQ VSS+.4 +100 mA A A V V A 2, 3 2, 3 4 1 mA 1 mA 1 Units Notes
IDD 25
x36 average power supply operating current (IOUT = 0, VIN = VIH or VIL)
IDD 27 IDD 30 IDD33 IDD 25
x18 average power supply operating current (IOUT = 0, VIN = VIH or VIL)
IDD 27 IDD 30 IDD33
Power supply standby current (R = VIH, W = VIH. All other inputs = VIH or VIH, IIH = 0) Input leakage current, any input (except JTAG) (VIN = VSS or VDD) Output leakage current (VOUT = VSS or VDDQ, Q in High-Z) Output "high" level voltage (IOH = -6mA) Output "low" level voltage (IOL = +6mA) JTAG leakage current (VIN = VSS or VDD) 1. IOUT = chip output current. 2. Minimum impedance output driver. 3. JEDEC Standard JESD8-6 Class 1 compatible. 4. For JTAG inputs only.
ISB ILI ILO VOH VOL ILIJTAG
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Integrated Silicon Solution, Inc.
Rev. A 05/14/09
Q72 Mb (2M x 36 & 4M x 18) QUADP (Burst of 4) Synchronous SRAMs
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Minimum VREF + 0.2 VREF - 0.2 VREF + 0.2 VREF - 0.2 Maximum Notes 1, 2, 3, 4 1, 2, 3, 4 1, 2, 3 1, 2, 3
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Typical AC Input Characteristics
Item AC input logic high AC input logic low Clock input logic high (K, K, C, C) Clock input logic low (K, K, C, C) 1. 2. 3. 4. Symbol VIH (ac) VIL (ac) VIH-CLK (ac) VIL-CLK (ac)
The peak-to-peak AC component superimposed on VREF may not exceed 5% of the DC component of VREF. Performance is a function of VIH and VIL levels to clock inputs. See the AC Input Definition diagram. See the AC Input Definition diagram. The signals should swing monotonically with no steps rail-to-rail with input signals never ringing back past VIH (AC) and VIL (AC) during the input setup and input hold window. VIH (AC) and VIL (AC) are used for timing purposes only.
AC Input Definition
K
VREF
K VRAIL VIH (AC) VREF
Setup Time
Hold Time
VIL (AC)
V-RAIL
Programmable Impedance Output Driver DC Electrical Characteristics
(TA = 0 to +70 C, VDD = 1.8V -5%, +5%, VDDQ = 1.5, 1.8V)
Parameter Output "high" level voltage Output "low" level voltage
VDDQ RQ
Symbol VOH VOL
Minimum VDDQ / 2 VSS
Maximum VDDQ VDDQ / 2
Units V V
Notes 1, 3 2, 3
1. IOH = ------------------ -------- 15% @ VOH = VDDQ / 2 For: 175 RQ 350. 2 5 VDDQ RQ 2. IOL = ------------------ -------- 15% @ VOL = VDDQ / 2 For: 175 RQ 350. 2 5
3. Parameter tested with RQ = 250 and VDDQ = 1.5V.
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Rev. A 05/14/09
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72 Mb (2M x 36 & 4M x 18) Q QUADP (Burst of 4) Synchronous SRAMs
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Symbol VDDQ VIH VIL VREF TR TF Conditions 1.5, 1.8 VREF+0.5 VREF-0.5 0.75, 0.9 0.35 0.35 VREF VREF Units V V V V ns ns V V 1, 2 Notes
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AC Test Conditions (TA = 0 to +70 C, VDD = 1.8V -5%, +5%, VDDQ = 1.5, 1.8V)
Parameter Output driver supply voltage Input high level Input Low Level Input reference voltage Input rise time Input fall time Output timing reference level Clocks reference level Output load conditions 1. See AC Test Loading. 2. Parameter tested with RQ = 250 and VDDQ = 1.5V.
AC Test Loading
50 Q 50 0.75, 0.9V Test Comparator
5pF 0.75, 0.9V
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Integrated Silicon Solution, Inc.
Rev. A 05/14/09
72 Mb (2M x 36 & 4M x 18) QUADP (Burst of 4) Synchronous SRAMs
AC CHARACTERISTICS (VDD = 1.8V 0.1V, TA=0 C to +70 C)
PARAMETER
Clock Clock Cycle Time (K, K) Clock Phase Jitter (K, K) Clock High Time (K, K) Clock Low Time (K, K) Clock to Clock (K, K) DLL Lock Time (K, K) Doff Low period to DLL reset Output Times K, K High to Output Valid K, K High to Output Hold K, K High to Echo Clock Valid K, K High to Echo Clock Hold CQ, CQ High to Output Valid CQ, CQ High to Output Hold K, High to Output High-Z K, High to Output Low-Z Setup Times Address valid to K rising edge Control inputs valid to K rising edge Data-in valid to K, K rising edge Hold Times K rising edge to address hold K rising edge to control inputs hold K, K rising edge to data-in hold Notes: 1. All address inputs must meet the specified setup and hold times for all latching clock edges. 2. Control singles are R, W,BW0,BW1 and (BW2, BW3, also for x36) 3. To avoid bus contention, at a given voltage and temperature tCHQX1 is bigger than tCHQZ. The specs as shown do not imply bus contention because tCHQX1 is a MIN parameter that is worst case at totally different test conditions (0 C, 1.9V) than tCHQZ, which is a MAX parameter (worst case at 70 C, 1.7V) It is not possible for two SRAMs on the same board to be at such different voltage and temperature. 4. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge. 5. Vdd slew rate must be less than 0.1V DC per 50ns for DLL lock retention. DLL lock time begins once Vdd and input clock are stable. 6. Echo clock is very tightly controlled to data valid/data hold. By design, there is a ns variation from echo clock to data. The data sheet parameters reflect tester guard bands and test setup variations tKHAX tKHIX tKHDX 0.40 0.40 0.28 0.40 0.40 0.28 0.40 0.40 0.28 0.40 0.40 0.28 tAVKH tIVKH tDVKH 0.40 0.40 0.28 0.40 0.40 0.28 0.40 0.40 0.28 0.40 0.40 0.28 ns ns ns ns ns ns ns 2 tKHKH tKC var tKHKL tKLKH tKHKH tKC lock
tDoffLowToReset
25 (400 MHz)
27 (375 MHz)
30 (333 MHz)
33 (300 MHz)
Min
2.50 0.40 0.40 1.06 2048 5
Max
7.5 0.20
Min
2.66 0.40 0.40 1.13 2048 5
Max
7.5 0.20
Min
3.00 0.40 0.40 1.28 2048 5
Max
7.5 0.20
Min
3.30 0.40 0.40 1.40 2048 5
Max
7.5 0.20
unit
ns ns cycles ns ns cycles ns
notes
4
5
tCHQV tCHQX tCHCQV tCHCQX tCQHQV tCQHQX tCHQZ tCHQX1 -0.45 -0.20 -0.45 -0.45
0.45 -0.45 0.45 -0.45 0.20 -0.20 0.45 -0.45
0.45 -0.45 0.45 -0.45 0.20 -0.20 0.45 -0.45
0.45 -0.45 0.45 -0.45 0.20 -0.20 0.45 -0.45
0.45
ns ns
0.45
ns ns
0.20 0.45
ns ns ns ns
6 6
Integrated Silicon Solution, Inc.
Rev. A 05/14/09
17
72 Mb (2M x 36 & 4M x 18) QUADP (Burst of 4) Synchronous SRAMs
Read and Deselect Cycles Timing Diagram
Read tKHKH tKHKL tKLKH K tKHKH K tAVKH
Read
NOP
NOP
tKHAX SA A1 tIVKH tKHIX R A2
Q (Data-Out)
Q1-1 tCHQV
Q1-2
Q1-3
Q1-4
Q2-1
Q2-2
Q2-3
Q2-4
tCHQX
tCHQZ
tCHCQX tCQHQV CQ tCHCQX CQ tCHCQV tCHCQV
tCQHQX
Don't Care
Undefined
Note: 1. Q1-1 refers to the output from address A1+0, Q1-2, Q1-3, Q1-4 refers to the output from address A1+1, A1+2, A1+3, which is the nex internal burst addresses following A1+0. 2. Outputs are disabled one cycle after a NOP.
18
Integrated Silicon Solution, Inc.
Rev. A 05/14/09
72 Mb (2M x 36 & 4M x 18) QUADP (Burst of 4) Synchronous SRAMs
Write and NOP Timing Diagram
Write tKHKH tKHKL K tKHKH K tAVKH SA A1 tIVKH W tKHIX A2 tKHAX Write NOP NOP
tKLKH
tKHIX
BWX
B1-1
B1-2
B1-3
B1-4
B2-1 tDVKH
B2-2
B2-3 tKHDX
B2-4
D (Data-In)
D1-1
D1-2
D1-3
D1-4
D2-1
D2-2
D2-3
Don't Care
D2-4
Undefined
NOTE: (B1-1 refers to all BWX byte controls for D1-1)
Integrated Silicon Solution, Inc.
Rev. A 05/14/09
19
72 Mb (2M x 36 & 4M x 18) QUADP (Burst of 4) Synchronous SRAMs
Read, Write, and NOP Timing Diagram
Read Write Read Write NOP NOP
K K SA BWX R W D (Data-In) D (Data-Out) D2-1 D2-2 D2-3 Q1-1 D2-4 Q1-2 D4-1 Q1-3 D4-2 Q1-4 D4-3 Q3-1 D4-4 Q3-2 Q3-3 Q3-4 A1 A2 A3 B2-1 B2-2 A4 B2-3 B2-4 B4-1 B4-2 B4-3 B4-4
CQ CQ
Note: If address A3=A2, data Q3-1=D2-1, data Q3-2=D2-2, data Q3-3=D2-3, and data Q3-4=D2-4, then write data is forwarded immediately as read results.
Don't Care
Undefined
20
Integrated Silicon Solution, Inc.
Rev. A 05/14/09
72 Mb (2M x 36 & 4M x 18) QQUADP (Burst of 4) Synchronous SRAMs
I
3
IEEE 1149.1 TAP and Boundary Scan The SRAM provides a limited set of JTAG functions to test the interconnection between SRAM I/Os and printed circuit board traces or other components. There is no multiplexer in the path from I/O pins to the RAM core. In conformance with IEEE Standard 1149.1, the SRAM contains a TAP controller, instruction register, boundary scan register, bypass register, and ID register. The TAP controller has a standard 16-state machine that resets internally on power-up. Therefore, a TRST signal is not required. Signal List * * * * TCK: test clock TMS: test mode select TDI: test data-in TDO: test data-out
JTAG DC Operating Characteristics (TA = 0 to +70 C) Operates with JEDEC Standard 8-5 (1.8V) logic signal levels
Parameter JTAG input high voltage JTAG input low voltage JTAG output high level JTAG output low level 1. 2. 3. All JTAG inputs and outputs are LVTTL-compatible. IOH1 = -2mA IOL1 = +2mA Symbol VIH1 VIL1 VOH1 VOL1 Minimum 1.3 -0.3 VDD-0.4 VSS Typical -- -- -- -- Maximum VDD+0.3 0.5 VDD 0.4 Units V V V V Notes 1 1 1, 2 1, 3
JTAG AC Test Conditions (TA = 0 to +70 C, VDD = 1.8V -5%, +5%)
Parameter Input pulse high level Input pulse low level Input rise time Input fall time Input and output timing reference level Symbol VIH1 VIL1 TR1 TF1 Conditions 1.3 0.5 1.0 1.0 0.9 Units V V ns ns V
Integrated Silicon Solution, Inc.
Rev. A 05/14/09
21
72 Mb (2M x 36 & 4M x 18) Q QUADP (Burst of 4) Synchronous SRAMs
I
Minimum 20 7 7 4 4 4 4 -- Maximum -- -- -- -- -- -- -- 7 Units ns ns ns ns ns ns ns ns 1 Notes
3
JTAG AC Characteristics (TA = 0 to +70 C, VDD = 1.8V -5%, +5%)
Parameter TCK cycle time TCK high pulse width TCk low pulse width TMS setup TMS hold TDI setup TDI hold TCK low to valid data 1. See AC Test Loading on page 16. Symbol tTHTH tTHTL tTLTH tMVTH tTHMX tDVTH tTHDX tTLOV
JTAG Timing Diagram
tTHTL tTLTH tTHTH
TCK
tTHMX
TMS tMVTH
tTHDX
TDI
tDVTH
TDO
tTLOV
22
Integrated Silicon Solution, Inc.
Rev. A 05/14/09
72 Mb (2M x 36 & 4M x 18) QUADP (Burst of 4) Synchronous SRAMs Q
I
Bit Size x18 or x36 3 1 32 109
3
Scan Register Definition
Register Name Instruction Bypass ID Boundary Scan
ID Register Definition
Field Bit Number and Description Part 4M x 18 2M x 36 Revision Number (31:29) 000 000 Part Configuration (28:12) 00def0wx0t0q0b0s0 00def0wx0t0q0b0s0 JEDEC Code (11:1) 000 101 001 00 000 101 001 00 Start Bit (0) 1 1
Part Configuration Definition: def = 011 for 72Mb wx = 11 for x36, 10 for x18 t = 1 for DLL, 0 for non-DLL q = 1 for QUADB4, 0 for DDR-II b = 1 for burst of 4, 0 for burst of 2 s = 1 for separate I/0, 0 for common I/O
Integrated Silicon Solution, Inc.
Rev. A 05/15/09
23
Q 72 Mb (2M x 36 & 4M x 18) QUADP (Burst of 4) Synchronous SRAMs
Instruction Set
Code 000 001 010 011 100 101 110 111 Instruction EXTEST IDCODE SAMPLE-Z PRIVATE SAMPLE PRIVATE PRIVATE BYPASS TDO Output Boundary Scan Register 32-bit Identification Register Boundary Scan Register Do not use Boundary Scan Register Do not use Do not use Bypass Register 1, 2 5 4 5 5 3 Notes 2,6
I
3
1. Places Qs in high-Z in order to sample all input data, regardless of other SRAM inputs. 2. TDI is sampled as an input to the first ID register to allow for the serial shift of the external TDI data. 3. BYPASS register is initiated to VSS when BYPASS instruction is invoked. The BYPASS register also holds the last serially loaded TDI when exiting the shift-DR state. 4. SAMPLE instruction does not place DQs in high-Z. 5. This instruction is reserved. Invoking this instruction will cause improper SRAM functionality. 6. This EXTEST is not IEEE 1149.1-compliant. By default, it places Q in high-Z. If the internal register on the scan chain is set high, Q will be updated with information loaded via a previous SAMPLE instruction. The actual transfer occurs during the update IR state after EXTEST is loaded. The value of the internal register can be changed during SAMPLE and EXTEST only.
List of IEEE 1149.1 Standard Violations * * * * * 7.2.1.b, e 7.7.1.a-f 10.1.1.b, e 10.7.1.a-d 6.1.1.d
JTAG Block Diagram
TDI
Bypass Register (1 bit) Identification Register (32 bits) Instruction Register (3 bits) TDO
Control Signals
TMS TCK
TAP Controller
24
Integrated Silicon Solution, Inc.
Rev. A 05/14/09
72 Mb (2M x 36 & 4M x 18) QUADP (Burst of 4) Synchronous SRAMs Q
I
3
TAP Controller State Machine
1
Test Logic Reset 0 0 Run Test Idle 1 Select DR 0 1 1 Capture DR 0 0 Shift DR 1 1 1 Exit1 DR 0 0 0 0 Pause IR 1 0 Exit1 IR 0 Shift IR 1 1 Select IR 0 Capture IR 0 1
Pause DR 1
Exit2 DR 0 1 1 Update DR 0 1
Exit2 IR 1 Update IR 0
Integrated Silicon Solution, Inc.
Rev. A 05/14/09
25
72 Mb (2M x 36 & 4M x 18) Q QUADP (Burst of 4) Synchronous SRAMs
I
Pin ID 10D 9E 10C 11D 9C 9D 11B 11C 9B 10B 11A 10A 9A 8B 7C 6C 8A 7A 7B 6B 6A 5B 5A 4A 5C 4B 3A 2A 1A 2B 3B 1C 1B 3D 3C 1D Order 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 Pin ID 2C 3E 2D 2E 1E 2F 3F 1G 1F 3G 2G 1H 1J 2J 3K 3J 2K 1K 2L 3L 1M 1L 3N 3M 1N 2M 3P 2N 2P 1P 3R 4R 4P 5P 5N 5R Internal
3
Boundary Scan Exit Order The same length is used for x18 and x36 I/O configuration.
Order 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Pin ID 6R 6P 6N 7P 7N 7R 8R 8P 9R 11P 10P 10N 9P 10M 11N 9M 9N 11L 11M 9L 10L 11K 10K 9J 9K 10J 11J 11H 10G 9G 11F 11G 9F 10F 11E 10E Order 37 37 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
Note: 1) NC pins as defined on FBGA pinouts on page 2 are read as "don't cares". 2) State of Internal pin (#109) is loaded via JTAG
26
Integrated Silicon Solution, Inc.
Rev. A 05/14/09
72 Mb (2M x 36 & 4M x 18) QUADP (Burst of 4) Synchronous SRAMs
NOTE :
1. Controlling dimension : mm
Integrated Silicon Solution, Inc.
Rev. A 05/14/09
Package Outline
12/10/2007
27
72 Mb (2M x 36 & 4M x 18) QUAD (Burst of 4) Synchronous SRAMs
ORDERING INFORMATION Commercial Range: 0C to +70C
Speed 400 MHz Order Part No. IS61QDPB42M36-400M3 IS61QDPB42M36-400M3L IS61QDPB44M18-400M3 IS61QDPB44M18-400M3L IS61QDPB42M36-375M3 IS61QDPB42M36-375M3L IS61QDPB44M18-375M3 IS61QDPB44M18-375M3L IS61QDPB42M36-333M3 IS61QDPB42M36-333M3L IS61QDPB44M18-333M3 IS61QDPB44M18-333M3L IS61QDPB42M36-300M3 IS61QDPB42M36-300M3L IS61QDPB44M18-300M3 IS61QDPB44M18-300M3L Organization 2Mx36 2Mx36 4Mx18 4Mx18 2Mx36 2Mx36 4Mx18 4Mx18 2Mx36 2Mx36 4Mx18 4Mx18 2Mx36 2Mx36 4Mx18 4Mx18 Package 165 BGA 165 BGA, Lead-free 165 BGA 165 BGA, Lead-free 165 BGA 165 BGA, Lead-free 165 BGA 165 BGA, Lead-free 165 BGA 165 BGA, Lead-free 165 BGA 165 BGA, Lead-free 165 BGA 165 BGA, Lead-free 165 BGA 165 BGA, Lead-free
375 MHz
333 MHz
300 MHz
28
Integrated Silicon Solution, Inc.
Rev. A 05/14/09

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